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1 From cbb97fe18e299ece1c0074924c630de6a19b320f Mon Sep 17 00:00:00 2001
2 From: Diederik de Haas <didi.debian@cknow.org>
3 Date: Sat, 6 Apr 2024 19:28:04 +0200
4 Subject: [PATCH] arm64: dts: rockchip: Fix ordering of nodes on rk3588s
5
6 Fix the ordering of the main nodes by sorting them alphabetically and
7 then the ones with a memory address sequentially by that address.
8
9 Signed-off-by: Diederik de Haas <didi.debian@cknow.org>
10 Link: https://lore.kernel.org/r/20240406172821.34173-1-didi.debian@cknow.org
11 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
12 ---
13 arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 304 +++++++++++-----------
14 1 file changed, 152 insertions(+), 152 deletions(-)
15
16 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
17 +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
18 @@ -347,6 +347,11 @@
19 };
20 };
21
22 + display_subsystem: display-subsystem {
23 + compatible = "rockchip,display-subsystem";
24 + ports = <&vop_out>;
25 + };
26 +
27 firmware {
28 optee: optee {
29 compatible = "linaro,optee-tz";
30 @@ -394,11 +399,6 @@
31 #clock-cells = <0>;
32 };
33
34 - display_subsystem: display-subsystem {
35 - compatible = "rockchip,display-subsystem";
36 - ports = <&vop_out>;
37 - };
38 -
39 timer {
40 compatible = "arm,armv8-timer";
41 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
42 @@ -436,6 +436,62 @@
43 };
44 };
45
46 + gpu: gpu@fb000000 {
47 + compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
48 + reg = <0x0 0xfb000000 0x0 0x200000>;
49 + #cooling-cells = <2>;
50 + assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
51 + assigned-clock-rates = <200000000>;
52 + clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
53 + <&cru CLK_GPU_STACKS>;
54 + clock-names = "core", "coregroup", "stacks";
55 + dynamic-power-coefficient = <2982>;
56 + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
57 + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
58 + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
59 + interrupt-names = "job", "mmu", "gpu";
60 + operating-points-v2 = <&gpu_opp_table>;
61 + power-domains = <&power RK3588_PD_GPU>;
62 + status = "disabled";
63 +
64 + gpu_opp_table: opp-table {
65 + compatible = "operating-points-v2";
66 +
67 + opp-300000000 {
68 + opp-hz = /bits/ 64 <300000000>;
69 + opp-microvolt = <675000 675000 850000>;
70 + };
71 + opp-400000000 {
72 + opp-hz = /bits/ 64 <400000000>;
73 + opp-microvolt = <675000 675000 850000>;
74 + };
75 + opp-500000000 {
76 + opp-hz = /bits/ 64 <500000000>;
77 + opp-microvolt = <675000 675000 850000>;
78 + };
79 + opp-600000000 {
80 + opp-hz = /bits/ 64 <600000000>;
81 + opp-microvolt = <675000 675000 850000>;
82 + };
83 + opp-700000000 {
84 + opp-hz = /bits/ 64 <700000000>;
85 + opp-microvolt = <700000 700000 850000>;
86 + };
87 + opp-800000000 {
88 + opp-hz = /bits/ 64 <800000000>;
89 + opp-microvolt = <750000 750000 850000>;
90 + };
91 + opp-900000000 {
92 + opp-hz = /bits/ 64 <900000000>;
93 + opp-microvolt = <800000 800000 850000>;
94 + };
95 + opp-1000000000 {
96 + opp-hz = /bits/ 64 <1000000000>;
97 + opp-microvolt = <850000 850000 850000>;
98 + };
99 + };
100 + };
101 +
102 usb_host0_ehci: usb@fc800000 {
103 compatible = "rockchip,rk3588-ehci", "generic-ehci";
104 reg = <0x0 0xfc800000 0x0 0x40000>;
105 @@ -501,62 +557,6 @@
106 status = "disabled";
107 };
108
109 - gpu: gpu@fb000000 {
110 - compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
111 - reg = <0x0 0xfb000000 0x0 0x200000>;
112 - #cooling-cells = <2>;
113 - assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
114 - assigned-clock-rates = <200000000>;
115 - clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
116 - <&cru CLK_GPU_STACKS>;
117 - clock-names = "core", "coregroup", "stacks";
118 - dynamic-power-coefficient = <2982>;
119 - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
120 - <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
121 - <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
122 - interrupt-names = "job", "mmu", "gpu";
123 - operating-points-v2 = <&gpu_opp_table>;
124 - power-domains = <&power RK3588_PD_GPU>;
125 - status = "disabled";
126 -
127 - gpu_opp_table: opp-table {
128 - compatible = "operating-points-v2";
129 -
130 - opp-300000000 {
131 - opp-hz = /bits/ 64 <300000000>;
132 - opp-microvolt = <675000 675000 850000>;
133 - };
134 - opp-400000000 {
135 - opp-hz = /bits/ 64 <400000000>;
136 - opp-microvolt = <675000 675000 850000>;
137 - };
138 - opp-500000000 {
139 - opp-hz = /bits/ 64 <500000000>;
140 - opp-microvolt = <675000 675000 850000>;
141 - };
142 - opp-600000000 {
143 - opp-hz = /bits/ 64 <600000000>;
144 - opp-microvolt = <675000 675000 850000>;
145 - };
146 - opp-700000000 {
147 - opp-hz = /bits/ 64 <700000000>;
148 - opp-microvolt = <700000 700000 850000>;
149 - };
150 - opp-800000000 {
151 - opp-hz = /bits/ 64 <800000000>;
152 - opp-microvolt = <750000 750000 850000>;
153 - };
154 - opp-900000000 {
155 - opp-hz = /bits/ 64 <900000000>;
156 - opp-microvolt = <800000 800000 850000>;
157 - };
158 - opp-1000000000 {
159 - opp-hz = /bits/ 64 <1000000000>;
160 - opp-microvolt = <850000 850000 850000>;
161 - };
162 - };
163 - };
164 -
165 pmu1grf: syscon@fd58a000 {
166 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
167 reg = <0x0 0xfd58a000 0x0 0x10000>;
168 @@ -702,74 +702,6 @@
169 status = "disabled";
170 };
171
172 - vop: vop@fdd90000 {
173 - compatible = "rockchip,rk3588-vop";
174 - reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
175 - reg-names = "vop", "gamma-lut";
176 - interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
177 - clocks = <&cru ACLK_VOP>,
178 - <&cru HCLK_VOP>,
179 - <&cru DCLK_VOP0>,
180 - <&cru DCLK_VOP1>,
181 - <&cru DCLK_VOP2>,
182 - <&cru DCLK_VOP3>,
183 - <&cru PCLK_VOP_ROOT>;
184 - clock-names = "aclk",
185 - "hclk",
186 - "dclk_vp0",
187 - "dclk_vp1",
188 - "dclk_vp2",
189 - "dclk_vp3",
190 - "pclk_vop";
191 - iommus = <&vop_mmu>;
192 - power-domains = <&power RK3588_PD_VOP>;
193 - rockchip,grf = <&sys_grf>;
194 - rockchip,vop-grf = <&vop_grf>;
195 - rockchip,vo1-grf = <&vo1_grf>;
196 - rockchip,pmu = <&pmu>;
197 - status = "disabled";
198 -
199 - vop_out: ports {
200 - #address-cells = <1>;
201 - #size-cells = <0>;
202 -
203 - vp0: port@0 {
204 - #address-cells = <1>;
205 - #size-cells = <0>;
206 - reg = <0>;
207 - };
208 -
209 - vp1: port@1 {
210 - #address-cells = <1>;
211 - #size-cells = <0>;
212 - reg = <1>;
213 - };
214 -
215 - vp2: port@2 {
216 - #address-cells = <1>;
217 - #size-cells = <0>;
218 - reg = <2>;
219 - };
220 -
221 - vp3: port@3 {
222 - #address-cells = <1>;
223 - #size-cells = <0>;
224 - reg = <3>;
225 - };
226 - };
227 - };
228 -
229 - vop_mmu: iommu@fdd97e00 {
230 - compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
231 - reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
232 - interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
233 - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
234 - clock-names = "aclk", "iface";
235 - #iommu-cells = <0>;
236 - power-domains = <&power RK3588_PD_VOP>;
237 - status = "disabled";
238 - };
239 -
240 uart0: serial@fd890000 {
241 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
242 reg = <0x0 0xfd890000 0x0 0x100>;
243 @@ -1140,6 +1072,87 @@
244 };
245 };
246
247 + av1d: video-codec@fdc70000 {
248 + compatible = "rockchip,rk3588-av1-vpu";
249 + reg = <0x0 0xfdc70000 0x0 0x800>;
250 + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
251 + interrupt-names = "vdpu";
252 + assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
253 + assigned-clock-rates = <400000000>, <400000000>;
254 + clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
255 + clock-names = "aclk", "hclk";
256 + power-domains = <&power RK3588_PD_AV1>;
257 + resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
258 + };
259 +
260 + vop: vop@fdd90000 {
261 + compatible = "rockchip,rk3588-vop";
262 + reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
263 + reg-names = "vop", "gamma-lut";
264 + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
265 + clocks = <&cru ACLK_VOP>,
266 + <&cru HCLK_VOP>,
267 + <&cru DCLK_VOP0>,
268 + <&cru DCLK_VOP1>,
269 + <&cru DCLK_VOP2>,
270 + <&cru DCLK_VOP3>,
271 + <&cru PCLK_VOP_ROOT>;
272 + clock-names = "aclk",
273 + "hclk",
274 + "dclk_vp0",
275 + "dclk_vp1",
276 + "dclk_vp2",
277 + "dclk_vp3",
278 + "pclk_vop";
279 + iommus = <&vop_mmu>;
280 + power-domains = <&power RK3588_PD_VOP>;
281 + rockchip,grf = <&sys_grf>;
282 + rockchip,vop-grf = <&vop_grf>;
283 + rockchip,vo1-grf = <&vo1_grf>;
284 + rockchip,pmu = <&pmu>;
285 + status = "disabled";
286 +
287 + vop_out: ports {
288 + #address-cells = <1>;
289 + #size-cells = <0>;
290 +
291 + vp0: port@0 {
292 + #address-cells = <1>;
293 + #size-cells = <0>;
294 + reg = <0>;
295 + };
296 +
297 + vp1: port@1 {
298 + #address-cells = <1>;
299 + #size-cells = <0>;
300 + reg = <1>;
301 + };
302 +
303 + vp2: port@2 {
304 + #address-cells = <1>;
305 + #size-cells = <0>;
306 + reg = <2>;
307 + };
308 +
309 + vp3: port@3 {
310 + #address-cells = <1>;
311 + #size-cells = <0>;
312 + reg = <3>;
313 + };
314 + };
315 + };
316 +
317 + vop_mmu: iommu@fdd97e00 {
318 + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
319 + reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
320 + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
321 + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
322 + clock-names = "aclk", "iface";
323 + #iommu-cells = <0>;
324 + power-domains = <&power RK3588_PD_VOP>;
325 + status = "disabled";
326 + };
327 +
328 i2s4_8ch: i2s@fddc0000 {
329 compatible = "rockchip,rk3588-i2s-tdm";
330 reg = <0x0 0xfddc0000 0x0 0x1000>;
331 @@ -1431,6 +1444,16 @@
332 reg = <0x0 0xfdf82200 0x0 0x20>;
333 };
334
335 + dfi: dfi@fe060000 {
336 + reg = <0x00 0xfe060000 0x00 0x10000>;
337 + compatible = "rockchip,rk3588-dfi";
338 + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
339 + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
340 + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
341 + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
342 + rockchip,pmu = <&pmu1grf>;
343 + };
344 +
345 pcie2x1l1: pcie@fe180000 {
346 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
347 bus-range = <0x30 0x3f>;
348 @@ -1533,16 +1556,6 @@
349 };
350 };
351
352 - dfi: dfi@fe060000 {
353 - reg = <0x00 0xfe060000 0x00 0x10000>;
354 - compatible = "rockchip,rk3588-dfi";
355 - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
356 - <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
357 - <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
358 - <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
359 - rockchip,pmu = <&pmu1grf>;
360 - };
361 -
362 gmac1: ethernet@fe1c0000 {
363 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
364 reg = <0x0 0xfe1c0000 0x0 0x10000>;
365 @@ -2543,19 +2556,6 @@
366 #interrupt-cells = <2>;
367 };
368 };
369 -
370 - av1d: video-codec@fdc70000 {
371 - compatible = "rockchip,rk3588-av1-vpu";
372 - reg = <0x0 0xfdc70000 0x0 0x800>;
373 - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
374 - interrupt-names = "vdpu";
375 - assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
376 - assigned-clock-rates = <400000000>, <400000000>;
377 - clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
378 - clock-names = "aclk", "hclk";
379 - power-domains = <&power RK3588_PD_AV1>;
380 - resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
381 - };
382 };
383
384 #include "rk3588s-pinctrl.dtsi"
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